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Abstract

A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input signal, and generates a delayed output signal from the input signal. The delay circuit also includes a second delay stage that receives the delayed output signal of the first delay stage, and generates a delayed output signal from the output of the first delay stage. The first delay stage and the second delay stage are coupled a voltage supply. The magnitude of the delay of the second delayed signal is inversely proportional to the magnitude of the supply voltage to substantially the same degree that the delayed output signal of the first delay stage is proportional to the magnitude of the supply voltage.

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