Instruction-assisted cache management for efficient use of cache and memory

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United States of America Patent

PATENT NO 7437510
APP PUB NO 20070079073A1
SERIAL NO

11241538

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Abstract

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Instruction-assisted cache management for efficient use of cache and memory. Hints (e.g., modifiers) are added to read and write memory access instructions to identify the memory access is for temporal data. In view of such hints, alternative cache policy and allocation policies are implemented that minimize cache and memory access. Under one policy, a write cache miss may result in a write of data to a partial cache line without a memory read/write cycle to fill the remainder of the line. Under another policy, a read cache miss may result in a read from memory without allocating or writing the read data to a cache line. A cache line soft-lock mechanism is also disclosed, wherein cache lines may be selectably soft locked to indicate preference for keeping those cache lines over non-locked lines.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lakshmanamurthy, Sridhar Sunnyvale, CA 63 1029
Rosenbluth, Mark Uxbridge, MA 31 642

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