Aligning multiple chip input signals using digital phase lock loops

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United States of America Patent

PATENT NO 8692596
SERIAL NO

14075084

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Abstract

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This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of clock signals at a plurality of clock pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted clock signal's reflected signal as a tuning reference.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cooke, Laurence H Los Gatos, US 103 3386

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