Selective address space refresh mode

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United States of America Patent

PATENT NO 6341097
SERIAL NO

09764654

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method and system of refreshing a DRAM having a multitude of successive wordlines. The method comprises the step of starting a refresh cycle, and this starting step includes the steps of (I) counting the wordlines one at a time in succession, (ii) refreshing the wordlines counted over a first period t1, and (iii) at the end of period t1, stopping the refreshing of the wordlines, and continuing the counting of the wordlines for a period t2. The method further comprises the step of, after period t2, restarting the refresh cycle. Preferably, the restarting step includes the steps of, at the end of period t2, delaying for a period t3; and restarting the refresh cycle at the end of period t3. The method may include the further step of adjusting the length of the period t1, and preferably, during the combined periods t1 and t2, all of the wordlines are counted. Also, preferably the processing unit determines the memory space to be refreshed; and, more specifically, this may be accomplished by the processing unit issuing a reset signal to terminate the refresh period t1.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hsu, Louis L Fishkill, NY 299 8481
Parent, Richard Michael Shelburne, VT 7 73
Wordeman, Matthew Robert Makawao, HI 5 122

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