Integrated chip multiplayer decoupling capacitors
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United States of America Patent
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Sep 26, 2000
Issued Date -
N/A
app pub date -
Dec 10, 1999
filing date -
Oct 6, 1995
priority date (Note) -
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Abstract
A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.
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