Semiconductor package having solder joint of improved reliability
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United States of America Patent
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Sep 11, 2007
Issued Date -
N/A
app pub date -
Mar 4, 2003
filing date -
May 10, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package mounted on a printed circuit board using improved-reliability solder joints is described. The semiconductor package includes a lead frame pad and lead frame lead attached to the solder joints, a semiconductor chip mounted on top of the lead frame pad, wires electrically connecting the semiconductor chip and the lead frame lead, an epoxy molding compound that exposes the lower portion surface of the lead frame pad and part of the lead frame lead, and protrusions fixed to the lower portion surface of the epoxy molding compound and positioned between the solder joints, with the protrusions supporting the semiconductor package when the epoxy molding compound is mounted on the printed circuit board.
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