Electric connection element manufacturing method

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United States of America Patent

PATENT NO 9460960
APP PUB NO 20160064278A1
SERIAL NO

14838976

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Abstract

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A surface of a silicon substrate is coated with a silicon oxide layer. A manganese silicate layer is then deposited on the silicon oxide layer using a process of performing at least one step of dipping the substrate into a manganese amidinate solution. A copper layer is then deposited on the manganese silicate layer using a process of performing a step of dipping the substrate into a copper amidinate solution. An anneal is performed to stabilize one or both of the manganese silicate layer and copper layer.

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Patent Owner(s)

  • CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE;STMICROELECTRONICS (TOURS) SAS

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chaudret, Bruno Vigoulet Auzil, FR 14 83
Cure, Jeremy Paris, FR 1 0
Fau, Pierre Toulouse, FR 3 41
Piettre, Kilian Linz, AT 5 0

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