Top drain MOSFET
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United States of America Patent
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Jan 29, 2008
Grant Date -
Sep 8, 2005
app pub date -
Jan 25, 2005
filing date -
Jan 26, 2004
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spaced trenches are formed in the top surface. One group of trenches contain gate polysilicon and a gate oxide to control an invertible channel region along the trench. A second group of the trenches have a buried source contact at their bottoms which are connected between the N source material to the P channel region to short out a parasitic bipolar transistor.
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