Layout for integrated circuit and the integrated circuit

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United States of America Patent

PATENT NO 11494543
APP PUB NO 20200285797A1
SERIAL NO

16883575

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Abstract

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A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jiang, Zhe-Wei Hsinchu, TW 23 255
Kao, Jerry Chang-Jui Taipei, TW 54 194
Lei, Cheok-Kei Andar, MO 22 287
Li, Yu-Chi Hsinchu, TW 8 7
Liu, Chi-Lin New Taipei, TW 58 151
Lu, Chi-Yu New Taipei, TW 92 154
Tseng, Chia-Wei Hsinchu, TW 8 1
Yang, Jung-Chan Taoyuan County, TW 87 129
Zhuang, Hui-Zhong Kaohsiung, TW 264 755

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