Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions
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United States of America Patent
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-
Jan 2, 1996
Issued Date -
N/A
app pub date -
Mar 19, 1993
filing date -
Oct 30, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A super scalar computer architecture and method of operation for executing instructions out-of-order while managing for data dependencies, data anti-dependencies, and integrity of sequentiality for precise interrupts, restarts and branch deletions. Multiple registers and tables are used to rename and recycle source and destination addresses referenced to a general purpose register. Access to destination data in the general purpose register is locked until the instruction associated with the data is fully executed. Renaming of both the source and destination registers avoids anti-dependency problems while integrity of sequentiality is maintained by ordered retirement of instruction results consistent with the order of the input instructions. The system and method operate with multiple input instructions and multiple execution units. The control words generated by the renaming of the source and destination registers differ insignificantly from the original instructions, obviating the practice of adding status and sequence information to processor control words.
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