No-precharge FAMOS cell and latch circuit in a memory device
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United States of America Patent
Stats
-
Aug 28, 2007
Grant Date -
Oct 26, 2006
app pub date -
Jun 22, 2006
filing date -
Jul 7, 2003
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The read circuit includes circuitry that reduces the drive strength of the fuse. A transmission gate couples the read circuit to the latch circuit. The transmission gate isolates the fuse from the latch. When a reset condition occurs, the data that was in latch circuit remains after the reset condition is complete.
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