Dynamic program erase targeting with bit error rate

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United States of America Patent

PATENT NO 11361825
APP PUB NO 20210193229A1
SERIAL NO

16719745

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Abstract

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A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Koudele, Larry J Erie, US 109 759
Liikanen, Bruce A Berthoud, US 140 1274
Sheperek, Michael Longmont, US 99 324

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