IC package with capacitors disposed on an interposal layer
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United States of America Patent
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Sep 3, 2013
Issued Date -
N/A
app pub date -
Jul 20, 2011
filing date -
Jan 20, 2009
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.
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