Biasing scheme for improving latitudes in the tri-level xerographic process
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United States of America Patent
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Jan 14, 1992
Grant Date -
N/A
app pub date -
Nov 22, 1989
filing date -
Nov 22, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The operating latitude of the tri-level xerographic process is improved by replacing the standard DC bias that is applied to one or both of the developer housings in conventional tri-level imaging with a chopped DC (CDC) developer bias. Chopped DC biasing is the alternate application of two discrete bias voltages to a developer stucture in a periodic fashion at a given frequency, with the period of each cycle divided up between the two bias levels at a duty cycle of from 5%-10% or 90%-95% depending upon which of the two developer structures is being biased. In the case of the DAD developer structure the duty cycle of higher of the two biases is 5%-10% and in case of a CAD developer structure the duty cycle of higher of the two biases is 90%-95%.
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