Process integration for flash storage element and dual conductor complementary MOSFETs
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United States of America Patent
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Jun 12, 2012
Grant Date -
Jan 20, 2011
app pub date -
Sep 13, 2010
filing date -
Apr 28, 2008
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Abstract
A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction can be deposited simultaneously with a first metal layer for forming the floating gate of the flash storage element. A second gate metal layer of the PFET having a second workfunction different from the first workfunction can be deposited simultaneously with a second metal layer for forming the control gate of the flash storage element. A semiconductor layer can then be deposited over the first and second metal layers and gate metal layers and patterned to form first, second and third gates. Source and drain regions of the flash storage element, the NFET and the PFET can then be formed adjacent to the first, second and third gates, respectively.
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