Flash memory device capable of preventing program disturbance according to partial programming
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United States of America Patent
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Feb 27, 2007
Grant Date -
Oct 21, 2004
app pub date -
Apr 5, 2004
filing date -
Aug 28, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A non-volatile semiconductor memory device disclosed herein includes arrays of memory cells arranged along rows and columns. The columns are divided into at least two column regions and each row is divided into two electrically isolated word lines that are arranged in the column regions. The memory device further includes a determining circuit for judging which column region a data loaded on a register belongs to during a program operation, and a selecting circuit for choosing one of the rows in response to the row address information and driving one or all of the word lines in the selected row with a program voltage according to the judging.
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