Negative gate erase
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 23, 2001
Grant Date -
N/A
app pub date -
Feb 28, 2001
filing date -
Feb 28, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
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