Programming and erasing structure for a floating gate memory cell and method of making

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United States of America Patent

PATENT NO 7183161
APP PUB NO 20060063328A1
SERIAL NO

10944244

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Abstract

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A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

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Patent Owner(s)

  • NXP USA, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chindalore, Gowrishankar L Austin, TX 66 908
Swift, Craig T Austin, TX 47 575

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