Interleaved testing of digital and analog subsystems with on-chip testing interface

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United States of America Patent

PATENT NO 11531061
SERIAL NO

16983938

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The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

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Patent Owner(s)

  • QUALCOMM INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Raghuraman, Praveen Chennai, IN 14 149

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