Processor and chipset continuity testing of package interconnect for functional safety applications
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United States of America Patent
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Nov 1, 2022
Grant Date -
Sep 16, 2021
app pub date -
May 31, 2021
filing date -
Jun 27, 2018
priority date (Note) -
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Abstract
Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.
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