Multi-gate III-V quantum well structures

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United States of America Patent

PATENT NO 8344425
APP PUB NO 20110156004A1
SERIAL NO

12655463

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Abstract

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Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chau, Robert S Beaverton, US 514 18995
Dewey, Gilbert Hillsboro, US 439 4103
Kavalieros, Jack Portland, US 270 9074
Metz, Matthew V Portland, US 331 5773
Mukherjee, Niloy Beaverton, US 230 3780
Pillarisetty, Ravi Portland, US 449 7359
Radosavljevic, Marko Beaverton, US 465 4716
Rakshit, Titash Hillsboro, US 91 1417
Shah, Uday Portland, US 159 4609

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