Method and apparatus for wordline redundancy control of memory in an information handling system
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United States of America Patent
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Sep 9, 2008
Grant Date -
Jan 17, 2008
app pub date -
Jul 14, 2006
filing date -
Jul 14, 2006
priority date (Note) -
Expired
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Abstract
A memory system including a memory array with redundant wordlines. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.
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