Scalable logic self-test configuration for multiple chips
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United States of America Patent
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Dec 5, 2006
Grant Date -
Jul 14, 2005
app pub date -
Jan 8, 2004
filing date -
Jan 8, 2004
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple clock domains and/or multiple chips to be controlled from a common point.
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