Processes of forming stacked resistor constructions
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United States of America Patent
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Dec 19, 2006
Grant Date -
Mar 24, 2005
app pub date -
Oct 4, 2004
filing date -
Oct 2, 2002
priority date (Note) -
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Abstract
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.
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