Method and device for verification of VLSI designs
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United States of America Patent
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May 20, 2003
Grant Date -
Oct 3, 2002
app pub date -
Mar 30, 2001
filing date -
Mar 30, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention provides a formal equivalence verification method and system to determine the compatibility, or nonsimilarity, of two or more circuit designs. The method and system can check the corresponding verification nodes or candidates for cut points while accounting for input vectors including environmental conditions. The method and system may produce an answer for the user to indicate, for example, compatibility or disimilarity.
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