Method of enabling selective area plating on a substrate

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United States of America Patent

PATENT NO 7891091
APP PUB NO 20100126009A1
SERIAL NO

12315066

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Abstract

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A method of enabling selective area plating on a substrate (201) includes forming a first electrically conductive layer (310) on the substrate, covering the electrically conductive layer with an anti-electroless plating layer (410), patterning the substrate in order to form therein a feature (510, 520) extending through the anti-electroless plating layer and the first electrically conductive layer, forming a second electrically conductive layer (610) adjoining and electrically connected to the first electrically conductive layer, forming a third electrically conductive layer (710) over the second electrically conductive layer, and removing the anti-electroless plating layer and the first electrically conductive layer.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Yonggang 343 W. Canary Way 77 390
Salama, Islam 4435 E. Cherry Hill Dr. 27 268

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