Ultra-high speed imaging array with orthogonal readout architecture
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United States of America Patent
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Sep 9, 2014
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Apr 10, 2014
app pub date -
Oct 10, 2012
filing date -
Oct 10, 2012
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Abstract
A plurality of unit pixels in a two dimensional imaging array are arranged in a manner that signal charges along a given row are added to other relevant signal charges of the same row. Signal charges along a given column are added to other relevant signal charges of the same column. Summed charge values are output simultaneously from rows and columns to produce one row and one column of image data. The resulting summed data is temporarily stored in on-chip buffers and then output from the chip during the integration time of the next imaging cycle with no loss in imaging duty cycle.
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