Compile device, compile method, and non-transitory computer readable medium for increasing a speed of a program
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United States of America Patent
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Nov 28, 2023
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N/A
app pub date -
Oct 11, 2019
filing date -
Dec 7, 2018
priority date (Note) -
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Abstract
A vector load instruction generating unit of a compile device generates an instruction to load a “first group of data units”, which is used as an element A[i] in iterative calculation processing, from a memory into a first vector register in a state of being packed in units of 1-word. Each data unit is (1/2)k word. The vector load instruction generating unit generates an instruction to load a second group of data units, which is used as an element [i+2k] into a second vector register. A vector shift double instruction generating unit generates an instruction to cause a part of a data string, which is obtained by shifting data of the first vector Register and the second register by (1/2)k word as a series of data string, to be stored in a third vector register in a state of being packed in units of 1-word.
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