Method for fabricating semiconductor device

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United States of America Patent

PATENT NO 7521305
APP PUB NO 20060160341A1
SERIAL NO

11140952

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Abstract

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A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

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Patent Owner(s)

  • INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Cha-Hsin Hsinchu , TW 41 479
Lu, Shing-Chii Hsinchu , TW 6 30
Pei, Zing-Way Hsinchu , TW 18 81
Tsai, Ming-Jinn Hsinchu , TW 21 319

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