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Abstract

Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles, the timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.

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First Claim