Process for fabricating short channel field effect transistor with a highly conductive gate
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United States of America Patent
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Apr 24, 2001
Grant Date -
N/A
app pub date -
Jun 3, 1998
filing date -
Jun 3, 1998
priority date (Note) -
Expired
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Abstract
Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.
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- 15 United States
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Patent Owner(s)
- INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Furukawa, Toshiharu | Essex Junction, VT | 317 | 7067 |
Hakey, Mark C | Milton, VT | 172 | 4277 |
Holmes, Steven J | Milton, VT | 316 | 5608 |
Horak, David V | Essex Junction, VT | 328 | 7709 |
Nakos, James S | Essex Junction, VT | 57 | 868 |
Rabidoux, Paul A | Winooski, VT | 38 | 1240 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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