Process for fabricating short channel field effect transistor with a highly conductive gate

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United States of America Patent

PATENT NO 6221704
SERIAL NO

09089650

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Furukawa, Toshiharu Essex Junction, VT 317 7067
Hakey, Mark C Milton, VT 172 4277
Holmes, Steven J Milton, VT 316 5608
Horak, David V Essex Junction, VT 328 7709
Nakos, James S Essex Junction, VT 57 868
Rabidoux, Paul A Winooski, VT 38 1240

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