Method of monitoring system bus traffic by a CPU operating with reduced power
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United States of America Patent
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Sep 15, 1998
Issued Date -
N/A
app pub date -
Apr 2, 1997
filing date -
Dec 23, 1994
priority date (Note) -
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Abstract
The present invention provides a method for maintaining cache coherency while minimizing the power consumption. The method includes operating a first processor in a reduced power mode. While the first processor is operating in a reduced power mode, certain portions of the internal logic in the first processor remain clocked so that the first processor continues to monitor transactions on the system bus. The second processor runs a transaction on the system bus to request data. In the event that the first processor determines that the transaction by the second processor is requesting cache data that is stored in the first processor in a modified state, the first processor signals the second processor. After the current bus cycle is completed, the first processor writes back the modified cache line on the system bus and second processor re-runs the transaction on the system bus.
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