Memory controller with staggered request signal output

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United States of America Patent

PATENT NO 11830573
APP PUB NO 20220343956A1
SERIAL NO

17705039

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Abstract

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A memory device includes a first receive circuit to receive a control signal of a memory access request from a memory controller. A second receive circuit receives a timing signal from the memory controller. The memory device includes circuitry to transmit, during a calibration mode of operation, feedback to the memory controller along a data path, the feedback indicative of a phase relationship been the control signal and the timing signal.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCSAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lau, Benedict C San Jose, US 52 1431
Shaeffer, Ian P Los Gatos, US 97 943
Stott, Bret Menlo Park, US 20 177

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