Memory including side-car arrays with irregular sized entries
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United States of America Patent
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Jun 4, 2019
Grant Date -
Jul 26, 2018
app pub date -
Jan 26, 2017
filing date -
Jan 26, 2017
priority date (Note) -
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Abstract
A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.
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