Importance

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Abstract

A zero power standby bias system controls the standby voltage levels of a current reference system used as a sense amplifier read reference in a non-volatile memory. The memory includes a non-volatile memory array having a plurality of memory cells coupled to bit lines. A plurality of sense amplifiers are coupled to the bit lines to determine the values stored in the memory cells in comparison to the reference signal provided by the reference system. The comparator circuit is not limited to a reference current, but can use reference voltages and a bit line voltage. The zero power standby bias system maintains a voltage level of the reference system to levels near those of operation while in standby mode, eliminating the need for the circuit to overcome large voltage differences and capacitance transitioning from low power or standby mode to active. The zero power standby bias system, therefore, eliminates overhead and speeds initial access times for non-volatile memory cells.

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First Claim