Importance

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Abstract

A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The secondary interconnect trunk intersects the primary interconnect trunk at an intersection at which a bus control element is located. The bus control element includes a primary trunk interface that couples to the primary interconnect trunk at the intersection to enable the bus control element to control on-chip communication among the compute elements via coherency signals on the primary interconnect trunk. The bus control element includes a secondary trunk interface coupled to the secondary interconnect trunk.

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First Claim