Buffer control circuit of memory device
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United States of America Patent
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Sep 1, 2020
Grant Date -
N/A
app pub date -
Dec 13, 2018
filing date -
Aug 14, 2018
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device includes a target clock generation circuit suitable for generating a target clock by dividing a frequency of an internal clock at a set ratio, a delay circuit suitable for generating first to Nth delay clocks having first to Nth pulse widths that gradually increase, in synchronization with the target clock, a flag detection circuit suitable for filtering the first to Nth delay clocks based on the target clock to generate first to Nth flag signals and decoding the first to Nth flag signals to generate first to (N−1)th current control signals, and a buffer circuit suitable for adjusting an amount of current based on the first to (N−1)th current control signals, and buffering an externally inputted signal using the adjusted amount of current.
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