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Abstract

A programmable semiconductor memory circuit comprises a memory cell array, a write circuit which is driven by a first power source voltage only in a write mode for writing data into memory cells of the memory cell array, an address input circuit which is driven by a second power source voltage for supplying an address signal to the memory cell array, and an input level correcting circuit supplied with the first power source voltage only in the write mode for supplying the first power source voltage to the address input circuit. The second power source voltage has a voltage higher in the write mode than in a read mode. The address input circuit has an arrangement such that an input threshold value thereof changes when the second power source voltage changes. The input level correcting circuit supplies the first power source voltage to the address input circuit to pull up a signal level at an input of the address input circuit in the write mode so that a signal having a high logic level at the input of the address input circuit is greater than the input threshold value of the address input circuit.

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First Claim