Delay circuit of delay-locked loop circuit and delay-locked loop circuit
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United States of America
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May 10, 2022
Grant Date -
Jan 6, 2022
app pub date -
Jan 14, 2021
filing date -
Jan 14, 2021
priority date (Note) -
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Abstract
A delay circuit of a delay-locked loop (DLL) circuit includes: a phase splitter configured to split a phase of a reference clock signal to output a first reference clock signal and a second reference clock signal having a phase difference of 180 degrees; a logic gate configured to delay the second reference clock signal to output a delayed reference clock signal; and a delay line circuit including a plurality of delay cells that are cascade-connected, the delay line circuit configured to delay the first reference clock signal and the delayed reference clock signal based on a control code set, and to output a first delayed clock signal and a second delayed clock signal having a delay amount corresponding to a delay of one logic gate included in the plurality of delay cells.
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