Shared error correction for memory design
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United States of America Patent
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Dec 9, 2003
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N/A
app pub date -
Feb 4, 2000
filing date -
Feb 4, 2000
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Abstract
A shared error correcting circuit reduces memory overhead by sharing a fixed number of ECC bits among two or more memory units in a semiconductor memory. A single ECC block is used to generate check bits and syndrome bits. The ECC block tests each of the memory units by using the total number of ECC bits available in the ECC cells. Thus, the memory overhead is reduced from that in standard ECC designs.
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