Integrated memory device, method of operating an integrated memory, and memory system having a plurality of integrated memories
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United States of America Patent
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Jun 15, 2004
Grant Date -
Apr 3, 2003
app pub date -
Oct 1, 2002
filing date -
Oct 1, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An integrated memory has a selection circuit for setting a selectable latency--relative to a clock signal between a beginning of a read access and the provision of the data to outside the memory. A detection circuit compares data to be output with desired data and serves for setting the latency depending on the comparison result. The selection circuit receives a control signal, by means of which the latency can be set. In the event of noncorrespondence between the data read out and the desired data, the latency is increased by the detection circuit. This enables an accurate and error-free on-chip setting of a so-called CAS latency for a read-out operation of the memory.
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