Structure and design structure having isolated back gates for fully depleted SOI devices
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United States of America Patent
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Aug 10, 2010
Grant Date -
Dec 10, 2009
app pub date -
Jun 10, 2008
filing date -
Jun 10, 2008
priority date (Note) -
Expired
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Abstract
Methods, structure and design structure having isolated back gates for fully depleted semiconductor-on-insulator (FDSOI) devices are presented. In one embodiment, a method may include providing a FDSOI substrate having a SOI layer over a buried insulator over a first polarity-type substrate, the first polarity-type substrate including a second polarity-type well therein of opposite polarity than the first polarity; forming a trench structure in the FDSOI substrate; forming an active region to each side of the trench structure in the SOI layer; and forming a PFET on the active region on one side of the trench structure and an NFET on the active region on the other side of the trench structure.
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