Re-quantization in downlink receiver bit rate processor
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United States of America Patent
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Jan 22, 2013
Grant Date -
Apr 3, 2008
app pub date -
Sep 28, 2006
filing date -
Sep 28, 2006
priority date (Note) -
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Abstract
A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
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