Partitioned cache memory with switchable access paths
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United States of America Patent
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Mar 18, 2003
Issued Date -
N/A
app pub date -
May 8, 1998
filing date -
Dec 12, 1994
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Abstract
An information processing device includes a central processing unit, a cache memory unit and first and second decision circuits. The first decision circuit identifies one of partitioned address areas to be accessed before the central processing unit accesses the cache memory unit. The second decision circuit determines whether the above one of the partitioned address areas is a cachable area or a non-cachable area before address tag data is referred to in the cache memory unit.
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