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Abstract

On a surface of a silicon substrate having conductivity type of p-type, a field oxide layer and a gate oxide layer to be an isolation region are formed. A gate electrode is formed via the gate oxide layer. A surface silicon oxide layer is formed on a surface of the gate electrode. An etch stop layer is formed at a region outside of the surface silicon oxide layer, which etch stop layer is formed of a material different from a material of the gate oxide layer. Also, on the upper surface of the etch stop layer, an interlayer insulation layer is formed. Then, on the surface of the silicon substrate in the vicinity of the end of the gate electrode, an n.sup.- -diffusion layer is formed. In a region outside of the n.sup.--diffusion layer, an n.sup.+ -diffusion layer is formed. On the other hand, between the upper surface of the n.sup.- -diffusion layer and the n.sup.+ -diffusion layer and the lower end of the etch stop layer, a bottom silicon oxide layer having greater layer thickness than the gate oxide layer is formed. A wiring and the n.sup.+ -diffusion layer are connected each other via the contact hole formed in the interlayer insulation layer.

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