Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors
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United States of America Patent
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Sep 18, 2007
Grant Date -
Sep 30, 2004
app pub date -
Mar 9, 2004
filing date -
Mar 25, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.
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