Self-enabling pulse-trapping circuit
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United States of America Patent
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Nov 3, 1998
Issued Date -
N/A
app pub date -
Aug 19, 1997
filing date -
Dec 23, 1994
priority date (Note) -
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Abstract
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.
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