Signal generating method for clock recovery and clock recovery circuit
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United States of America Patent
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Mar 26, 2013
Grant Date -
Mar 17, 2011
app pub date -
Apr 22, 2009
filing date -
May 30, 2008
priority date (Note) -
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Abstract
According to the present invention, as shown in FIG. 5(a), when a signal for clock recovery ED is generated, which is formed by alternately generating enable periods EN having a ratio (N/M) of N clocks' client data to M clocks' line data and disable periods D1 to D4, a phase of the disable period D2 is advanced by a phase corresponding to the disable period (such as one clock period) during the enable period with reference to phase information added to the signal for clock recovery ED as shown in FIG. 5(c) when a stuff pulse in the line data is detected as indicated by the symbol m0 in FIG. 5(b), thereby generating the signal for clock recovery ED.
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