Compensating for DRAM activation penalties
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United States of America Patent
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Jan 2, 2024
Grant Date -
N/A
app pub date -
Feb 9, 2022
filing date -
Aug 13, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
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