Methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile
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United States of America Patent
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Aug 7, 2001
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N/A
app pub date -
May 12, 1998
filing date -
May 12, 1998
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Abstract
A hard resist layer is formed on and/or within a deep-UV configured resist mask prior to patterning a semiconductor device feature. The hard resist layer reduces the amount of polymer residue generated during the patterning process, which can effect the resulting profile of the device feature. The hard resist mask is formed by either ion implantation or plasma treatments. Due to the formation of the hard resist layer, the thickness of the resist mask can be reduced, thereby increasing the resolution capabilities of the resist mask.
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